1. Field of the Invention
The present invention relates in general to a three-dimensional charge coupled device (CCD) image sensor, and more particularly to a three-dimensional CCD image sensor having a silicon on insulator (SOI) structure for enhancing a resolution of the screen.
2. Description of the Prior Art
Generally, a CCD is an active device for transferring, under the control of a clock pulse, a signal charge corresponding to incident light incoming along a predetermined path and has typically been used in image processing devices, such as, for example, storage devices, logic elements, CCD image sensors and similar devices.
A CCD image sensor is generally formed by disposing a plurality of photodetectors and a plurality of CCDs as a photoscanner on a substrate of a semi-conductor material, such as silicon oxide. For the purpose of increasing the resolution of the CCD image sensor, it is preferable to design the area of the CCD, and particularly, a vertical charge coupled device (VCCD) to be as small as possible such that the effective area of the photodetector is relatively larger. It is particularly preferable in the CCD image sensor of an interline transfer type in which VCCDs are disposed between columns of the photodetector.
For instance, the photodetector may be a PN junction device, a metal insulator semi-conductor (MIS) device, a Schottky junction device and etc.
The scanning of the CCD image sensor employing the CCD as a photoscanner may be of an interlaced scanning type or a non-interlaced scanning type.
In the non-interlaced scanning, there is provided one picture, i.e., one frame containing a plurality of fields, with the scanning on the screen beginning with data in the first input field, as shown in FIG. 1a.
In FIG. 1a, the displays of each of fields on the screen in its input order are designated with the numerals 1, 2, 3, . . . .
On the other hand, in interlaced scanning, there is provided one frame containing a plurality of even fields and a plurality of odd fields, with the scanning on the screen beginning with data in the odd field, as shown in FIG. 1b.
In FIG. 1b, the numeral 1 designates each of the odd fields and the numeral 2 designates each of the even fields.
Therefore, in the non-interlaced scanning, the scanning rate is fast such that the actual image of a fast moving object can be picked up accurately. For this reason, the non-interlaced scanning may be applied to a military equipment, such as a missile.
However, a problem with this non-interlaced scanning is that the image shakes on the screen.
For interlaced scanning, there is provided a sense of stability of the image in that the scanning rate is slower than that in the non-interlaced scanning, but a fast moving object appears as two images. For this reason, interlaced scanning is inappropriate to a military purpose and typically applied to a TV broadcasting system, such as a NTSC system or a PAL system, for the scanning of image on the screen.
Now, a construction of a conventional CCD image sensor of the interlaced scanning type will be described with reference to FIGS. 2a through 2d.
Referring to FIG. 2a, there is shown a schematic diagram of a construction of the conventional CCD image sensor of the interlaced scanning type. The conventional CCD image sensor comprises a N type VCCD and a plurality of N type VCCDs, to each of which a series of N type photodiodes PDs are connected. The output of each of the N type photodiodes PDs is connected to the N type VCCD such that an image signal charge outputted therefrom is transferred to the N type VCCD in a single direction. Also, the N type VCCDs are connected to the N type HCCD such that the signal charges transferred from the photodiodes PDs are transferred to the N type HCCD simultaneously in response to first to fourth VCCD clock signals V.phi.1-V.phi.4, one clock signal corresponding to one phase.
Referring to FIG. 2b, there is shown a layout diagram of the construction of the conventional CCD image sensor in FIG. 2a. The CCD image sensor comprises a channel stop region CST formed between each of the N type VCCDs and each of the N type photodiodes PD. An odd gate electrode PG1 is formed over each of the N type VCCDs and each of the channel stop regions CSTs such that it is connected to each of transfer gates TG1s of the N type photodiodes PD arranged in an odd horizontal line, the odd gate electrode PG1 being applied with the first and the second clock signals V.phi.1-V.phi.2. On the other hand, an even gate electrode PG2 is formed over each of the channel stop regions CSTs, each of the N type VCCDs and each of the N type photodiodes PD such that it is connected to each of transfer gates TG2s of the N type photodiodes PD arranged in an even horizontal line, the even gate electrode PG2 being applied with the third and the fourth clock signals V.phi.3-V.phi.4.
The forming of the odd gate electrodes PG1 and the even gate electrodes PG2 may be repeated successively, as they are required, in the same form. Also, these electrodes PG1 and PG2 are generally electrically isolated from each other by a region (not shown) of an insulating material, such as silicon oxide.
On the other hand, a material of the transfer gates TG1 and TG2 and the odd and even gate electrodes PG1 and PG2 may be polysilicon.
The odd gate electrode PG1 includes a first odd gate electrode PG1a formed under each of the N type photodiodes PD in the odd horizontal line and a second odd gate electrode PG1b formed over each of the N type photodiodes PD in the odd horizontal line and connected to each of the transfer gates TG1s of the photodiodes PD in the odd horizontal line, the first odd gate electrode PG1a being supplied with the second VCCD clock signal V.phi.2 and the second odd gate electrode PG1b being supplied with the first VCCD clock signal V.phi.1.
The even gate electrode PG2 includes a first even gate electrode PG2a formed under each of the N type photodiodes PD in the even horizontal line and a second even gate electrode PG2b formed over each of the N type photodiodes PD in the even horizontal line and connected to each of the transfer gates TG2s of the photodiodes PD in the even horizontal line, the first even gate electrode PG2a being applied with the fourth VCCD the second V.phi.4 and the second even gate electrode PG2b being applied with the third VCCD clock signal V.phi.3.
Also, the first through the fourth VCCD clock signals V.phi.1-V.phi.4 of four phases correspond to one of two fields, i.e. an even field or an odd field. The clocking operation of the N type VCCD will be described hereinafter in more detail.
Referring to FIG. 2c, there is shown a sectional view, taken on the line A--A' of FIG. 2b. The conventional CCD image sensor comprises a N type substrate 100 and a P type well 200, formed on the N type substrate 100. Also on the N type substrate 100 are configured a series of arrangements of the N type photodiodes PD and the N type VCCDs in even horizontal lines which are connected to each other at desired intervals via the channel stop region CST. Each of the transfer gates TG2 is formed over and between each of the N type photodiodes PD and its associated N type VCCDs to connect them with each other. Also over the surface of each of the N type VCCDs is formed the second even gate electrode PG2b of the even gate electrode PG2 which is supplied with the third VCCD clock signal V.phi.3, to be connected to each of the transfer gates TG2 of the N type photodiodes PD arranged in the even horizontal line.
Herein, the P type well 200 is comprised of two types, a shallow P type well 200a and a deep P type well 200b, for the control of over flow drain (OFD) voltage.
On the surface of each of the N type photodiodes PD is generally formed a P.sup.+ type thin layer 300 for the applying of an initial bias. In FIG. 2c, the lower side of the channel stop region CST designated as the character P.sup.+ indicates a channel stop ion.
Referring to FIG. 2d, there is shown a sectional view, taken on the line B--B' of FIG. 2b. The P type well 200 is formed on the N type substrate 100, identically to FIG. 2c. Also on the N type substrate 100 are configured several arrangements of N type photodiodes PD and the N type VCCDs in an even horizontal line which are connected to each other at desired intervals via the channel stop region CST. Also over the surface of each of the N type VCCDs is formed the first even gate electrode PG2a of the even gate electrode PG2 which is driven by the fourth VCCD clock signal V.phi.4. Similarly, on the surface of each of the N type photodiodes PD is generally formed the P.sup.+ type thin layer 300 for the applying an initial bias. In FIG. 2d, the lower side of the channel stop region CST, designated by the character P.sup.+ indicates a channel stop ion. Herein, the P type well 200 is comprised of the shallow P type well 200a and the deep P type well 200b, for the control of over flow drain (OFD) voltage.
Hence, the transfer gate TG1 of each of the N type photodiodes PD arranged in the odd horizontal line is driven only by the first VCCD clock signal V.phi.1 which is applied to the second odd gate electrode PG1b of odd gate electrode PG1, and the transfer gate TG2 of each of the N type photodiodes PD arranged in even horizontal line is driven only by the third VCCD clock signal V.phi.3 which is applied to the second even gate electrode PG2b of the even gate electrode PG2.
The second VCCD clock signal V.phi.2 being applied to the first odd gate electrode PG1a of the odd gate electrode PG1 and the fourth VCCD clock signal V.phi.4 being applied to the first even gate electrode PG2a of the even gate electrode PG2 serve merely to transfer image signal charges traveling from the N type photodiodes PD arranged in the odd and even horizontal lines toward the horizontal charge coupled device (HCCD).
The operation of the conventional CCD image sensor of the above-mentioned construction will now be described with reference to FIGS. 3a through 3c.
Referring to FIG. 3a, there is shown a timing diagram of the first through fourth VCCD clock signals V.phi.1-V.phi.4 of four phases, each including two fields, an even field and an odd field.
In this drawing, in the odd field of the first VCCD clock signal V.phi.1 being applied to the second odd gate electrode PG1b of the odd gate electrode PG1 is contained a high drive voltage signal V1 to the transfer gate. Also in the even field of the third VCCD clock signal V.phi.3 being applied to the second even gate electrode PG2b of the odd gate electrode PG2 is contained a high drive voltage signal V2 to the transfer gate.
First, if the first through fourth VCCD clock signals V.phi.1-V.phi.4 in the odd field are applied simultaneously, the transfer gates TG1s of the N type photodiodes PD arranged in each of the odd horizontal lines are turned on simultaneously by the transfer gate drive voltage signal V1 contained in the first VCCD clock signal V.phi.1.
For this reason, the image signal charges produced from the N type photodiodes PD are transferred to the N type VCCDs and then toward the N type HCCD by the VCCD clocking operation.
Referring to FIG. 3b, there is shown a pulse waveform diagram of the first through fourth clock signals V.phi.1-V.phi.4 at the unit interval K of FIG. 3a. The image signal charges produced from the N type photodiodes PD are transferred vertically toward the N type HCCD by a series of clocking operations as shown in FIG. 3b.
At this time, the second VCCD clock signal V.phi.2 being applied through the first odd gate electrode PG1a of the odd gate electrode PG1 formed in the lower side of the odd horizontal line serves merely to transfer the image signal charges transferred from the N type photodiodes PD arranged in the even horizontal line by the first VCCD clock signal V.phi.1 to the N type HCCD, together with the first VCCD clock signal V.phi.1.
Thereafter, if the first through fourth VCCD clock signals V.phi.1-V.phi.4 in the even field in FIG. 3a are applied simultaneously, the transfer gates TG2 of the N type photodiodes PD arranged in each of the even horizontal lines are turned on simultaneously by the transfer gate drive voltage signals V2 contained in the third VCCD clock signal V.phi.3.
For this reason, the image signal charges produced from the N type photodiodes PD in the even horizontal line are transferred to the N type VCCDs and then toward the N type HCCD by the VCCD clocking operation as shown in FIG. 3a, in the same manner as those of the odd field.
At this time, the fourth VCCD clock signal V.phi.4 being applied through the first even gate electrode PG2a of the even gate electrode PG2 formed in the lower side of the even horizontal line serves merely to transfer the image signal charges transferred from the N type photodiodes PD arranged in the even horizontal line by the third VCCD clock signal V.phi.3 to the N type HCCD, together with the third VCCD clock signal V.phi.3.
As stated, the use of the VCCD clock signals of four phases has the effect of transferring the image signal charge in amount more than that of the VCCD clock signals of two phases.
As a result, as mentioned above, by utilizing VCCD clocking signals of four phases, i.e. the first through fourth VCCD clock signals V.phi.1-V.phi.4 as shown in FIG. 3a, the image signal charges from the N type photodiodes PD arranged in the odd horizontal line are first in sequence scanned on the screen through the N type VCCDs and then through the N type HCCD and then the image signal charges from the N type photodiodes PD arranged in the even horizontal line are in sequence scanned on the screen through the N type VCCDs and then through the N type HCCD.
As previously stated, the scanning of the CCD image sensor as mentioned above is usually referred to as an interlaced scanning type.
Referring to FIG. 3c, there is shown a pixel format of one picture, or one frame, the picture being comprised of pixels, each being displayed as the numerals 1 and 2, each designating the image signal charges from the N type photodiodes PD arranged in the odd and even horizontal lines as shown in FIG. 2a, respectively.
However, the conventional CCD image sensor of the above-mentioned interlaced scanning type has been used broadly in a TV broadcasting system, such as a NTSC system or a PAL system, but has a disadvantage, in that the VCCD area, which is irrelevant to the reception of the image signal, is given much more weight in the total chip area of the CCD image sensor since a VCCD is located at every column of the photodetector. In other words, because the photodetector, the VCCD and the HCCD are all on a two-dimensional plane, the fill factor, i.e., the area possessed by the photodetector portion is reduced relatively. Therefore, in conventional CCD image sensors, there is a limit to an increase in the resolution of the screen.